mirror of
https://github.com/ProjectDreamland/area51.git
synced 2024-11-01 11:11:47 +01:00
235 lines
7.5 KiB
C++
235 lines
7.5 KiB
C++
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//=========================================================================
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//
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// PS2_VIFGIF_INLINE.HPP
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//
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//=========================================================================
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#ifndef PS2_VIFGIF_INLINE_H
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#define PS2_VIFGIF_INLINE_H
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//=========================================================================
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//=========================================================================
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//=========================================================================
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// VIF
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//=========================================================================
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//=========================================================================
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//=========================================================================
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inline
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u32 VIF_Unpack ( s32 DestVUAddr,
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s32 NVectors,
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s32 Format,
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xbool Signed,
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xbool Masked,
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xbool AbsoluteAddress )
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{
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u32 VP;
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ASSERT(NVectors <= 255) ; // NVectors is only 8 bits
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VP = (u32)(DestVUAddr&0x0000FFFF);
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VP |= (u32)((NVectors<<16)&0x00FF0000);
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if( !AbsoluteAddress ) VP |= (1<<15);
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if( Signed == FALSE ) VP |= (1<<14);
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VP |= (((u32)(0x60|Format))<<24);
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if( Masked == TRUE ) VP |= 0x10000000;
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return VP;
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}
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//=========================================================================
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inline
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u32 VIF_SkipWrite( s32 NVectorsToWrite,
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s32 NVectorsToSkip )
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{
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ASSERT( (NVectorsToWrite>=0) && (NVectorsToSkip>=0) );
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s32 WL = NVectorsToWrite;
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s32 CL = NVectorsToWrite + NVectorsToSkip;
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return (u32)(CL|(WL<<8)) | (1<<24);
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}
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//=========================================================================
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inline
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void VIF_Mask ( u32* pVifData,
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s32 X0, s32 Y1, s32 Z0, s32 W0,
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s32 X1, s32 Y2, s32 Z1, s32 W1,
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s32 X2, s32 Y3, s32 Z2, s32 W2,
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s32 X3, s32 Y4, s32 Z3, s32 W3 )
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{
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u32 VP0;
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u32 VP1;
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VP0 =((u32)0x20 << 24);
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VP1 =(u32)((X0<< 0)|(Y1<< 2)|(Z0<< 4)|(W0<< 6)|
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(X1<< 8)|(Y2<<10)|(Z1<<12)|(W1<<14)|
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(X2<<16)|(Y3<<18)|(Z2<<20)|(W2<<22)|
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(X3<<24)|(Y4<<26)|(Z3<<28)|(W3<<30));
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pVifData[0] = VP0;
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pVifData[1] = VP1;
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}
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//=========================================================================
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//=========================================================================
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//=========================================================================
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// GIF
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//=========================================================================
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//=========================================================================
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//=========================================================================
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inline giftag::giftag ( void )
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{
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ASSERT( (((u32)this)&0x0F) == 0 );
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((u64*)this)[0] = 0;
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((u64*)this)[1] = 0;
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}
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//=========================================================================
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inline giftag::~giftag ( void )
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{
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}
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//=========================================================================
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inline void giftag::Build ( s32 Mode,
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s32 NRegs,
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s32 NLoops,
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xbool UsePrim,
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s32 PrimType,
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u32 PrimFlags,
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xbool aEOP )
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{
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((u64*)this)[0] = 0;
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((u64*)this)[1] = 0;
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MODE = Mode;
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NREG = NRegs;
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NLOOP = NLoops;
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PRE = (UsePrim)?(1):(0);
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PRIM = ((u32)PrimType) | (PrimFlags<<3);
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EOP = (aEOP)?(1):(0);
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}
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//=========================================================================
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inline void giftag::BuildImageLoad( s32 NBytes, xbool aEOP )
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{
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ASSERT( (NBytes>>4) <= 32767 );
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((u64*)this)[0] = 0;
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((u64*)this)[1] = 0;
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PRE = 0;
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PRIM = 0;
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MODE = GIF_MODE_IMAGE;
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NREG = 0;
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NLOOP = (NBytes>>4);
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EOP = (aEOP)?(1):(0);
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}
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//=========================================================================
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inline void giftag::Build2( s32 NRegs,
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s32 NLoops,
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s32 PrimType,
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u32 PrimFlags )
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{
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((u64*)this)[0] = 0;
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((u64*)this)[1] = 0;
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EOP = 1;
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PRE = 1;
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MODE = GIF_MODE_PACKED;
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NREG = NRegs;
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NLOOP = NLoops;
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PRIM = ((u32)PrimType) | (PrimFlags<<3);
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}
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//=========================================================================
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inline void giftag::BuildRegLoad( s32 NRegs, xbool aEOP )
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{
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((u64*)this)[0] = 0;
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((u64*)this)[1] = 0;
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MODE = 0;
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PRE = 0;
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PRIM = 0;
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NREG = 1;
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NLOOP = NRegs;
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EOP = (aEOP)?(1):(0);
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R00 = GIF_REG_AD;
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}
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//=========================================================================
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#define SR00 R00=aR00;
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#define SR01 R01=aR01;
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#define SR02 R02=aR02;
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#define SR03 R03=aR03;
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#define SR04 R04=aR04;
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#define SR05 R05=aR05;
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#define SR06 R06=aR06;
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#define SR07 R07=aR07;
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#define SR08 R08=aR08;
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#define SR09 R09=aR09;
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#define SR10 R10=aR10;
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#define SR11 R11=aR11;
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#define SR12 R12=aR12;
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#define SR13 R13=aR13;
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#define SR14 R14=aR14;
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#define SR15 R15=aR15;
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#define SETREGS { SR00 SR01 SR02 SR03 SR04 SR05 SR06 SR07 SR08 SR09 SR10 SR11 SR12 SR13 SR14 SR15 }
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inline void giftag::Reg ( u8 aR00, u8 aR01, u8 aR02, u8 aR03, u8 aR04, u8 aR05, u8 aR06, u8 aR07, u8 aR08, u8 aR09, u8 aR10, u8 aR11, u8 aR12, u8 aR13, u8 aR14, u8 aR15 ) SETREGS
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#undef SR15
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#define SR15
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inline void giftag::Reg ( u8 aR00, u8 aR01, u8 aR02, u8 aR03, u8 aR04, u8 aR05, u8 aR06, u8 aR07, u8 aR08, u8 aR09, u8 aR10, u8 aR11, u8 aR12, u8 aR13, u8 aR14 ) SETREGS
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#undef SR14
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#define SR14
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inline void giftag::Reg ( u8 aR00, u8 aR01, u8 aR02, u8 aR03, u8 aR04, u8 aR05, u8 aR06, u8 aR07, u8 aR08, u8 aR09, u8 aR10, u8 aR11, u8 aR12, u8 aR13 ) SETREGS
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#undef SR13
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#define SR13
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inline void giftag::Reg ( u8 aR00, u8 aR01, u8 aR02, u8 aR03, u8 aR04, u8 aR05, u8 aR06, u8 aR07, u8 aR08, u8 aR09, u8 aR10, u8 aR11, u8 aR12 )SETREGS
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#undef SR12
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#define SR12
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inline void giftag::Reg ( u8 aR00, u8 aR01, u8 aR02, u8 aR03, u8 aR04, u8 aR05, u8 aR06, u8 aR07, u8 aR08, u8 aR09, u8 aR10, u8 aR11 )SETREGS
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#undef SR11
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#define SR11
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inline void giftag::Reg ( u8 aR00, u8 aR01, u8 aR02, u8 aR03, u8 aR04, u8 aR05, u8 aR06, u8 aR07, u8 aR08, u8 aR09, u8 aR10 )SETREGS
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#undef SR10
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#define SR10
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inline void giftag::Reg ( u8 aR00, u8 aR01, u8 aR02, u8 aR03, u8 aR04, u8 aR05, u8 aR06, u8 aR07, u8 aR08, u8 aR09 )SETREGS
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#undef SR09
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#define SR09
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inline void giftag::Reg ( u8 aR00, u8 aR01, u8 aR02, u8 aR03, u8 aR04, u8 aR05, u8 aR06, u8 aR07, u8 aR08 )SETREGS
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#undef SR08
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#define SR08
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inline void giftag::Reg ( u8 aR00, u8 aR01, u8 aR02, u8 aR03, u8 aR04, u8 aR05, u8 aR06, u8 aR07 )SETREGS
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#undef SR07
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#define SR07
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inline void giftag::Reg ( u8 aR00, u8 aR01, u8 aR02, u8 aR03, u8 aR04, u8 aR05, u8 aR06 )SETREGS
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#undef SR06
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#define SR06
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inline void giftag::Reg ( u8 aR00, u8 aR01, u8 aR02, u8 aR03, u8 aR04, u8 aR05 )SETREGS
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#undef SR05
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#define SR05
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inline void giftag::Reg ( u8 aR00, u8 aR01, u8 aR02, u8 aR03, u8 aR04 )SETREGS
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#undef SR04
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#define SR04
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inline void giftag::Reg ( u8 aR00, u8 aR01, u8 aR02, u8 aR03 )SETREGS
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#undef SR03
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#define SR03
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inline void giftag::Reg ( u8 aR00, u8 aR01, u8 aR02 )SETREGS
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#undef SR02
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#define SR02
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inline void giftag::Reg ( u8 aR00, u8 aR01 )SETREGS
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#undef SR01
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#define SR01
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inline void giftag::Reg ( u8 aR00 )SETREGS
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#undef SR00
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#define SR00
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//=========================================================================
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#endif
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//=========================================================================
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