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RISC-V Fixes for 6.12-rc2

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* PERF_TYPE_BREAKPOINT now returns -EOPNOTSUPP instead of -ENOENT, which
   aligns to other ports and is a saner value.
 * The KASAN-related stack size increasing logic has been moved to a
   C header, to avoid dependency issues.
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Merge tag 'riscv-for-linus-6.12-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt:

 - PERF_TYPE_BREAKPOINT now returns -EOPNOTSUPP instead of -ENOENT,
   which aligns to other ports and is a saner value

 - The KASAN-related stack size increasing logic has been moved to a C
   header, to avoid dependency issues

* tag 'riscv-for-linus-6.12-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: Fix kernel stack size when KASAN is enabled
  drivers/perf: riscv: Align errno for unsupported perf event
This commit is contained in:
Linus Torvalds 2024-10-04 12:16:51 -07:00
commit 7943f06cfc
4 changed files with 11 additions and 7 deletions
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3
arch/riscv/Kconfig
View file

@ -777,8 +777,7 @@ config IRQ_STACKS
config THREAD_SIZE_ORDER
int "Kernel stack size (in power-of-two numbers of page size)" if VMAP_STACK && EXPERT
range 0 4
default 1 if 32BIT && !KASAN
default 3 if 64BIT && KASAN
default 1 if 32BIT
default 2
help
Specify the Pages of thread stack size (from 4KB to 64KB), which also

7
arch/riscv/include/asm/thread_info.h
View file

@ -13,7 +13,12 @@
#include <linux/sizes.h>
/* thread information allocation */
#define THREAD_SIZE_ORDER CONFIG_THREAD_SIZE_ORDER
#ifdef CONFIG_KASAN
#define KASAN_STACK_ORDER 1
#else
#define KASAN_STACK_ORDER 0
#endif
#define THREAD_SIZE_ORDER (CONFIG_THREAD_SIZE_ORDER + KASAN_STACK_ORDER)
#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
/*

4
drivers/perf/riscv_pmu_legacy.c
View file

@ -22,13 +22,13 @@ static int pmu_legacy_ctr_get_idx(struct perf_event *event)
struct perf_event_attr *attr = &event->attr;
if (event->attr.type != PERF_TYPE_HARDWARE)
return -EOPNOTSUPP;
return -ENOENT;
if (attr->config == PERF_COUNT_HW_CPU_CYCLES)
return RISCV_PMU_LEGACY_CYCLE;
else if (attr->config == PERF_COUNT_HW_INSTRUCTIONS)
return RISCV_PMU_LEGACY_INSTRET;
else
return -EOPNOTSUPP;
return -ENOENT;
}
/* For legacy config & counter index are same */

4
drivers/perf/riscv_pmu_sbi.c
View file

@ -309,7 +309,7 @@ static void pmu_sbi_check_event(struct sbi_pmu_event_data *edata)
ret.value, 0x1, SBI_PMU_STOP_FLAG_RESET, 0, 0, 0);
} else if (ret.error == SBI_ERR_NOT_SUPPORTED) {
/* This event cannot be monitored by any counter */
edata->event_idx = -EINVAL;
edata->event_idx = -ENOENT;
}
}
@ -556,7 +556,7 @@ static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig)
}
break;
default:
ret = -EINVAL;
ret = -ENOENT;
break;
}