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clk: x86: Move clk-pmc-atom register defines to include/linux/platform_data/x86/pmc_atom.h
Move the register defines for the Atom (Bay Trail, Cherry Trail) PMC clocks to include/linux/platform_data/x86/pmc_atom.h. This is a preparation patch to extend the S0i3 readiness checks in drivers/platform/x86/pmc_atom.c with checking that the PMC clocks are off on suspend entry. Note these are added to include/linux/platform_data/x86/pmc_atom.h rather then to include/linux/platform_data/x86/clk-pmc-atom.h because the former already has all the other Atom PMC register defines. Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/20240305105915.76242-2-hdegoede@redhat.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
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2 changed files with 14 additions and 12 deletions
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@ -11,23 +11,12 @@
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_data/x86/clk-pmc-atom.h>
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#include <linux/platform_data/x86/pmc_atom.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#define PLT_CLK_NAME_BASE "pmc_plt_clk"
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#define PMC_CLK_CTL_OFFSET 0x60
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#define PMC_CLK_CTL_SIZE 4
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#define PMC_CLK_NUM 6
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#define PMC_CLK_CTL_GATED_ON_D3 0x0
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#define PMC_CLK_CTL_FORCE_ON 0x1
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#define PMC_CLK_CTL_FORCE_OFF 0x2
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#define PMC_CLK_CTL_RESERVED 0x3
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#define PMC_MASK_CLK_CTL GENMASK(1, 0)
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#define PMC_MASK_CLK_FREQ BIT(2)
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#define PMC_CLK_FREQ_XTAL (0 << 2) /* 25 MHz */
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#define PMC_CLK_FREQ_PLL (1 << 2) /* 19.2 MHz */
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struct clk_plt_fixed {
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struct clk_hw *clk;
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struct clk_lookup *lookup;
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@ -43,6 +43,19 @@
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BIT_ORED_DEDICATED_IRQ_GPSC | \
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BIT_SHARED_IRQ_GPSS)
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/* External clk generator settings */
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#define PMC_CLK_CTL_OFFSET 0x60
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#define PMC_CLK_CTL_SIZE 4
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#define PMC_CLK_NUM 6
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#define PMC_CLK_CTL_GATED_ON_D3 0x0
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#define PMC_CLK_CTL_FORCE_ON 0x1
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#define PMC_CLK_CTL_FORCE_OFF 0x2
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#define PMC_CLK_CTL_RESERVED 0x3
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#define PMC_MASK_CLK_CTL GENMASK(1, 0)
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#define PMC_MASK_CLK_FREQ BIT(2)
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#define PMC_CLK_FREQ_XTAL (0 << 2) /* 25 MHz */
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#define PMC_CLK_FREQ_PLL (1 << 2) /* 19.2 MHz */
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/* The timers accumulate time spent in sleep state */
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#define PMC_S0IR_TMR 0x80
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#define PMC_S0I1_TMR 0x84
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